A high voltage IC for driving an inverter or the like is disclosed in, for example, Japanese Patent No. 3,384,399 (Patent Document 1) and Proc. Of ISPSD'04, p385, H. Akiyama, et al (Mitsubishi Electric Corporation) (Non-patent Document 1).
FIG. 9A is a diagram showing the circuit construction of a power portion of a motor controlling inverter disclosed in the Patent Document 1. A power device (IGBTs Q1 to Q6 and diodes D1 to D6) used to drive a three-phase motor Mo constitutes a bridge circuit, and has a power module structure accommodated in the same package. A main power source Vcc is normally set to a high voltage of DC 100 to 400V. Particularly, with respect to motor control for a vehicle such as an electric vehicle (EV), a hybrid electric vehicle (HEV) or the like, a main power source Vcc is set to a high voltage of DC 650V. When the high potential side of the main power source Vcc is represented by VCCH and the low potential side of the main power source Vcc is represented by VCCL, in order to drive IGBTs Q1 to Q3 connected to VCCH, the potential of the gate electrodes of IGBTs is set to a higher potential. Therefore, a photo coupler (PC) or a high voltage IC (HVIC: High Voltage Integrated Circuit) 90 is used for the driving circuit. An input/output terminal (I/O: Input/Output) of the driving circuit is normally connected to a microcomputer, and the overall control of the inverter is carried out by the microcomputer.
FIG. 9B is a block diagram showing the internal constituent unit of the high voltage IC (HVIC) used in FIG. 9A, which is disclosed in the Patent document 1.
The high voltage IC 90 shown in FIG. 9B is constructed by a control circuit (CU: control unit), gate driving circuits GDU (Gate Drive Unit) 4 to 6 with GND potential of low potential as reference potential, gate driving circuits GDU1 to GDU3 with floating potential of high potential as reference potential and a level shift circuit (LSU: Level Shift Unit). The control circuit CU receives/transmits signals from/to the microcomputer through the input/output terminal I/O and generates a control signal for indicating which IGBT of FIG. 9A should be turned on and which IGBT should be turned off. The gate driving circuits GDU (Gate Drive Unit) 4 to 6 drive IGBTs Q4 to Q6 connected to the low potential side VCCL of the main power source Vcc of FIG. 9A. The gate driving circuits GDU1 to DGU3 drive IGBTs Q1 to Q3 connected to the high potential side VCCH of the main power source Vcc of FIG. 9A. The level shift circuit LSU acts to mediate between the signal of the control circuit CU of the VCCL level and the signals of GDU1 to GDU3 (SIN1 to SIN3, SOUT1 to SOUT3) going and returning between the VCCH level and the VCCL level. Accordingly, as described above, the semiconductor device constituting the level shift circuit LSU of the high voltage IC 90 treats the signal between the VCCH level and the VCCL level (0 to 650V), and thus particularly a withstanding voltage (about 1200V) is required.
As in the case of the high voltage IC 90 shown in FIG. 9B, in the semiconductor device in which two or more circuits having different reference potentials are integrated, the forming areas of the respective circuits having the different reference potentials are separated from each other by pn-junction separation or dielectric-material separation using dielectric material such as SiO2 or the like. With respect to the high voltage IC using the pn-junction separation, it is known that a parasitic transistor is easily formed and thus malfunction of the circuit or breakdown of elements may be induced. On the other hand, with respect to the high voltage IC using the dielectric-material separation, no parasitic transistor operation occurs, and thus there does not occur any problem such as malfunction of the circuit and the breakdown of elements.
FIG. 10 is a cross-sectional view showing a conventional high voltage IC 91 using an SOI substrate and trench separation.
In the high voltage IC 91 shown in FIG. 10, an SOI layer 1 of the SOI substrate 10 having an embedded oxide film 3 is provided with a low-potential (GND) reference circuit, a high-potential (float) reference circuit and a level shift circuit. The respective forming areas of the GND reference circuit, the float reference circuit and the level shift circuit are insulation-separated (dielectric-material separation) by the embedded oxide film 3 of the SOI substrate 10 and the side wall oxide film 4s of trenches 4.
In the level shift circuit of the high voltage IC 91, a circuit element having a high withstanding voltage is required to connect the low-potential reference circuit and the high-potential reference circuit to each other. An MOS type transistor TrL of the level shift circuit forming area shown in FIG. 10 has a SOI-RESURF structure to secure a withstanding voltage.
As shown in FIG. 10, the high voltage in the level shift circuit is applied to the drain (D) of the MOS type transistor TrL. In the MOS type transistor TrL of FIG. 10, the withstanding voltage in the lateral direction in section is secured by the SOI-RESURF structure including a surface p-type impurity layer and the embedded oxide film 3. With respect to the withstanding voltage in the longitudinal direction in section, a high voltage applied between the drain (D) and the ground (GND) is divided by a low-concentration SOI layer 1 and an embedded oxide film 3 to moderate the electric field in the SOI layer 1 as disclosed in Non-patent Document 1.
As described above, in order to implement a semiconductor device having a high withstanding voltage by using a semiconductor substrate having an SOI structure, it is required to optimally design the concentration and thickness of the SOI layer and the thickness of the embedded oxide film so that a desired withstanding voltage is achieved by distributing an applied voltage in the longitudinal direction in section to the SOI layer and the embedded oxide film.
However, when a high voltage of 1000V or more is achieved according to this method, the embedded oxide film of 5 μm or more in thickness and the SOI layer of 50 μm or more in thickness are needed. On the other hand, the upper limit of the achievable thickness of the embedded oxide film is equal to about 4 μm in consideration of warp, etc. of the SOI substrate. Furthermore, the thickness of the SOI layer is normally equal to several μm to about 20 μm, and as the thickness of the SOI layer is increased, the trench processing load is increased. Therefore, with respect to the MOS type transistor TrL in the level shift circuit forming area of FIG. 10, the achievable withstanding voltage is limited to about 600V, and thus it is impossible to secure a withstanding voltage of 1200V which is required in a 400V power supply system, an EV vehicle or the like.